Wearing Flip-Flops

Nobody enjoys opening a waveform viewer at 11pm. So here's the question this episode starts with: if AI reads the simulation database directly and does the root cause analysis for you, how much time are you actually spending in waves a year from now? Predrag Nikolic, AI Tech Lead at Veriest, thinks a lot less, and he is careful to say he hopes so rather than knows so. The logic is worth following. A waveform viewer is a human debug...

In episode 8 we host Sirish Kumar Munipalli, Co-Founder and CTO of MooresLabAI, an AI company building agentic automation for chip design verification and debug.

What we cover:
Build vs buy for AI verification tooling: when it makes sense for a DV team to build its own agents, and when that turns into a second product you never wanted to maintain.
Where AI actually earns its place today in functional verification and ...

Simulation runtime stops scaling long before your gate count does. Somewhere past a few hundred million gates, the weekend regression becomes the critical path, and the decision to move to emulation stops being academic.

In this episode we host Frank Schirrmeister, Executive Director of Strategic Programs, System Solutions at Synopsys, who has worked across emulation and hardware-assisted verification for most of his career.

What we ...

Simulation runtime stops scaling long before your gate count does. Somewhere past a few hundred million gates, the weekend regression becomes the critical path, and the decision to move to emulation stops being academic.

In this episode we host Frank Schirrmeister, Executive Director of Strategic Programs, System Solutions at Synopsys, who has worked across emulation and hardware-assisted verification for most of his career.

Wha...

Are we paying a massive "productivity tax" on today’s complex SOC verification just because the industry chose UVM over Specman ?

Look down at your keyboard. The only reason it starts with Q-W-E-R-T-Y is because 19th-century mechanical typewriters would jam if typists went too fast. It was literally designed to slow you down. The Dvorak keyboard layout was demonstrably faster and more ergonomic, yet QWERTY completely d...

We’re jumping back in for part two of the SOC Hyperscale playbook with Claudio to see how 26 years of experience at Amazon translates to the high-stakes world of silicon verification. While our last chapter laid the groundwork for scaling, this session gets into the "make or break" decisions that every manager eventually faces in the trenches. We transition from broad strategy to the gritty reality of the lab, where Claudio h...

Chip design verification isn't just about finding bugs, it's about managing massive-scale risk. Today, we’re hosting Claudio, Verification Manager for Amazon’s Graviton team, to discuss the reality of verifying hyperscale silicon.

We’re cutting through the noise to answer the core questions: What actually makes a 'good' verification plan? How do you know when you’re truly ready to tapeout? And how do you hand...