May 29, 2025 • 36 mins
Pratyush Kamal explains how 3DIC technologies are transforming semiconductor design as Moore's Law slows, requiring closer integration between chip and package design to maximize performance.
• Traditional chip design treated packaging as an afterthought with designers "throwing designs over the wall"
• Economic realities of advanced nodes mean companies now pay more for smaller transistors, driving chiplet adoption
• Thermal challenges multiply in 3D stacks as power density doubles with each added layer
• Data centers projected to consume 10% of US electricity by 2030, making power efficiency critical
• Siemens working to standardize design languages across tools and enable open chiplet ecosystems
• Average age of electrical engineers in US is 57, creating urgent need for workforce development
• Universal Chiplet Interconnect Express (UCIe) emerging as key standard for chiplet interoperability
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Transcript
Episode Transcript
Available transcripts are automatically generated. Complete accuracy is not guaranteed.
Francoise von Trapp (00:02):
Looking to stay ahead in the chiplet
revolution.
With 3DICs transformingeverything from AI to mobile and
data center design, Siemens EDAis making it easier than ever
to manage complexity andaccelerate innovation.
Their comprehensive 3DICsolution brings together
architecture, exploration,thermal analysis, verification
and co-design all in one unifiedplatform.
(00:24):
If you're navigating multi-diesystems, this is the competitive
edge you've been waiting for.
Visit siemenscom slash 3DIC tolearn more.
Hi there, I'm Francoise vonTrapp, and this is the 3D
(00:45):
Insights Podcast.
Hi everyone, you know if we'veheard it once, we've heard it a
hundred times on this podcast.
3dic using advanced packagingtechnologies are critical to
achieving power, performancearea and cost of next generation
semiconductor devices, and itreally looks like that next
(01:08):
generation that we've beentalking about for so long is
actually here.
It's now.
Design engineers know it andthey need the support of the EDA
or the electronic designautomation segment of the
industry.
So here to talk to me aboutthis important topic is Pratyush
Kamal.
He's the 3D IC expert, whohappens to work at Siemens
Digital Industries Software.
(01:30):
Welcome to the podcast,Pratyush.
Pratyush Kamal (01:32):
Thank you, Francoise, for having me here.
Francoise von Trapp (01:35):
So, before we dive in, can you tell me a
little bit about your backgroundand your current role at
Siemens and previous roles thatbrought you to this point?
Pratyush Kamal (01:44):
Sure, Francoise.
So I joined Siemens roughly twoyears ago.
I joined as a contractor,helping Siemens on their
government engagements,especially DARPA-driven projects
, and then for the last one yearI've been a full-time employee
and in my current role I'm theDirector of Central Engineering
Solutions and our charter isreally to look at a holistic
(02:04):
solution for 3D ICs as well asanything any new technologies
that is evolving when we talkabout two nanometer and below
nodes, because they really aretied to, as far as the usage
goes, advanced packaging in someform or the other very
intricately.
So that's the focus of ourcurrent organization.
It's a new team that has beenput together and we have a lot
(02:26):
of subject matter experts,people with different design
domain expertise, and I'm,overall, the technical lead for
this organization.
And prior to joining Siemens, Ihad many, many years of
experience.
I started my career as a designengineer, Then I grappled with
EDA industry for a while.
Engineer, then I grappled withEDA industry for a while and
(02:48):
then I spent 15 plus yearsdesigning chips and also
defining architecture for thechips as well as the systems.
I spent a lot of my career atQualcomm, a bit at Google as
well.
It's at Qualcomm, 10 plus yearsago that I first got introduced
to 3D IC and at the time wewere trying to look at a
long-term view of 3DIC howeventually, you know, when we
look at CFET and stacktechnologies of the future.
(03:09):
We were thinking about it 10years ago, but we realized the
challenges that lay ahead, so weshifted our focus on
stacked-based 3DIC, and a greatexample of that is a hybrid
bond-based wafer-on-wafer orchip-on-wafer stack.
So we picked that as ourresearch vehicle, but it didn't
prevent us from looking at other3D stack-based integration
(03:30):
options.
Francoise von Trapp (03:31):
So you know, when I first got into this
industry in 2005, I've alwaysfound the design side of things
to be very hard for me to grasp.
I have an easier time with thephysical, you know, and seeing
how things are structured.
And I remember talking to someof the experts when Siemens was
mentor and they were juststarting to look at co-design
(03:54):
and co-design optimization andthis is 20 years ago.
And how has that conversationchanged?
What kind of brought thatrealization that now it's all
this time and you're justdeveloping this actual team to
focus on that in the 3DIC space?
But can you explain a littlebit how that evolution occurred?
Pratyush Kamal (04:16):
The way I look at it, it almost seems like we
put this industry as anafterthought.
We first discovered thetransistor.
We manually learned to lay thattransistor.
All the words we continue touse today, they are all related
to manual processes, for example, tape out.
There was an actual tape thatwas involved in the tape out.
So we did everything manual.
(04:37):
And then one day some of usthought, okay, let's actually
try to automate that.
Then we built some tools.
We started putting more andmore complex circuits together.
As long as we were dealing withhundreds of thousands, the need
for automation was still small.
But the moment we shifted totrue VLSI, very large scale
integration, where you'redealing with millions and
millions, and today we arelooking at trillion transistor
(04:59):
designs Then we realized wecan't do everything manually and
over the years the industrydrove itself to automation.
That evolution happened.
But again, if you look at thewhole chip design process, it's
very complex.
It requires expertise from somany different fields.
Just the definition of atransistor requires multiple
expertise, right, and the amountof analysis the software needed
(05:20):
to do that is very diverse innature, and so that's one reason
why the way the EDA industrytoday is.
The design flows are veryfragmented.
For the many years now we havetalked about RTL to GDS,
holistic flows, and if you lookat the big EDA organizations,
they all have competingsolutions in the whole domain,
starting all the way from yourabstract definition of your
(05:43):
system, whether it's System C orwhatever, and bringing it all
the way down to the GDS that yousend to the foundry.
Right, this whole RTL to GDS, infact it's not even RTL, it's
behavioral to GDS.
Now we are talking, right,there are so many different
pieces of software involved hereand they have to be stitched
together over the years, formingwhat I call a patchwork,
(06:03):
quilted approach to designautomation.
So, yeah, it has been a lot ofover-the-wall approach because,
again, the expertise is sodiverse through this whole
process.
But as the complexitiesincrease and as new tools become
available to us tools likeartificial intelligence, that's
the case in point here we canstart to bring some of these
(06:24):
boundaries down, walls down.
We can start to imagineourselves as cross-functional
experts, even though we don'thave that background.
But we have these tools at ourdisposal today that will
tomorrow allow us to me, as anelectrical engineer, can
tomorrow dream to do mechanicalsimulations.
So that's what we are trying todo in 3D IC of today across the
(06:45):
industry.
Francoise von Trapp (06:46):
So you're saying what drove this is the
need for developing these inhigher volumes.
The devices are now in such avolume that it can't be done
manually.
But what if, when they startedthinking about not just chip
design and designing reallycomplex chips, but when they
started realizing that you notonly had to think about the chip
(07:09):
, you also had to think aboutthe package and the system and
maybe work it all the way backso that what you're designing in
a chip was going to be able tobe carried through?
Pratyush Kamal (07:20):
Yeah, I mean until very recently, if we take
the very high performancecompute market out, because it's
always spearheading in terms ofneeds by very definition.
But my previous experience wasin the mobile space and I'll
tell you anecdotally, as asilicon designer, we never
thought about the package.
It was an afterthought.
We designed our GDS, we threwit over the wall and then
(07:40):
somebody put a mold around itand it worked.
Right right and then somebodyput a mold around it and it
worked Right.
Right, as we started tothrottle up our speeds,
interface speeds, as our powerdensities increased, we started
to see challenges.
So then I mean, even today,most of the package design is
done in Windows environment.
Roughly 10 years ago was thefirst time I actually opened a
package layout in an EDA tool.
(08:02):
I wouldn't name the EDA toolinvolved there, but for the
first time I actually botheredto look at a layout, and the
reason for it was because I wasthe interface architect and we
had SI challenges on thatinterface and it was not a very
high speed interface.
We were talking PCIe 3.0 here,very small compared to PCIe 6.0
that we are starting to see.
(08:23):
You know, at least in thespecification space we are
discussing those.
What caught me by surprise wasthat it was actually a
Windows-based software.
I had never dealt with aWindows-based interface in
Silicon design world.
It came as a shock Then.
That's when I realized howdifferent package design and how
uncoupled it is from theSilicon world and how uncoupled
(08:45):
it is from the silicon world.
And today, as our team looks atco-design and looks at how we
can design these chiplets intandem because they will be used
in tandem in an advancedpackage tomorrow.
We have started to realize thegaps that exist.
You have to do a lot of dataconversion.
You have to not only do that,you have to move data across
different servers, differentfile formats and file servers.
(09:12):
So we are trying to bridge todecoupled world here through 3D
IC engagement Okay.
Francoise von Trapp (09:15):
So it's a very complex challenge to solve,
and so I can see where, earlyon, if you had manual that works
, if, until it was volume, therewas no need for EDA.
So it always seemed to me, likeyou know, you knew something
was approachingcommercialization if suddenly
there was an EDA tool for it.
Right In the beginning, when itwas still in R&D, until the EDA
(09:37):
tool came along, you knew thatsomething that was manufactured
in volumes.
But now everything's hopping ina little more close together.
We don't seem to be waiting aslong to engage the EDA vendors.
It seems to be more part of theholistic approach.
Is that true?
Pratyush Kamal (09:55):
That is true, and the reason for it again, is
the complexity of design.
What people realized is thatthe EDA industry evolves in
steps.
There'll be innovation and thenthere would be nothing for the
next few years, and thensomething new will come up.
Everybody will jump on thebandwagon and we will evolve,
and then the cadence is slow inthat sense.
Right the place and route tool.
Fundamentally, if you look atthe core algorithm, it hasn't
(10:18):
changed.
It has evolved.
The fundamental algorithm isstill the same as it was 25
years ago and you're very right.
Bang on on making thatassumption that when the EDA
tools appear, you have anindication of what is coming in
terms of actual end product.
I'll tell you a direct 3D ICanecdotal story that I have.
So I was part of QualcommResearch and we were working
(10:40):
with TSMC at the time, who wereusing hybrid band 3D-based 3D
stack for camera-basedapplications, image sensing
applications.
So we had an idea how we canexpand this to logic-on-logic 3D
application, make it completelygeneric, right?
So we built a couple of testchips.
We did not have any CAD toolsavailable to us, so we had to
(11:04):
hack everything ourselves and wespoke to a couple of EDA
companies at the time on behalfof Qualcomm and we did not get a
lot of collaboration becausethey wanted to first see whether
there was any product on theroadmap, whether there was a
path to commercialization forthis technology.
And we realized very soon thatwe don't have the budget to
spend tens of millions ofdollars just for tool
(11:27):
development when we have a fewthousands of dollars for the
product development as part ofthe R&D.
So we had to shelve our 3D ICFfor our ambitions 10 plus years
ago because of that limitation.
What has changed in the last 10years is A end of scaling On
paper.
We are still scaling things.
We are going from 5 to 4 to 3to 2 nanometer, but you're not
(11:48):
getting the same dimensionalshrink Plus.
You're not getting iteconomically.
You're actually paying more tobuild a smaller transistor,
unlike in the past.
Francoise von Trapp (11:58):
It seems like it's just being able to say
that we can do it.
It's not really about Moore'slaw anymore, it's that can we
keep scaling down, but then youalso have to look at packaging
that right.
Pratyush Kamal (12:09):
Yeah, I'll tell you why.
That packaging becomes verycritical for smaller technology
Because it's a very complexprocess.
The whole way for stackformation is much, much, much
more complex.
We are starting to use EUV.
Formation is much, much, muchmore complex.
We are starting to use UV.
We will be very shortly usinghigh-end UV-based solutions for
lithography.
The challenge is the industryhasn't yet fully understood the
(12:32):
defect mechanism through UV.
There is a lot of controlissues and we are talking about
22, 24 nanometer pitches here,and you can imagine the
stochastic challenges that wehave to deal with at that
geometry.
So what we are seeing is, eventhough we can yield designs in
these technology nodes, theyields are very poor, especially
(12:55):
as a dye size grows.
There is an exponentialcorrelation to the yield that
you'll get the larger the dye,the lower the yield.
So now, by definition, forthese technologies to be
economically feasible, you mustlimit your die size, otherwise
there'll be so many bad dies onyour wafer that it would not
make sense to you, and that'swhy the whole industry is moving
(13:19):
away from the idea of SOCsilicon on chip, where we talked
about a monolithic design whereall the functionality of the
system of the PCB goes insidethe die.
We are getting incrementalscaling advantage in these
technology nodes.
But there is other advantagethat drives the need for these
(13:39):
smaller to smaller nodesprimarily the performance and
power.
You may not be able to shrinkthe area as much, but you are
definitely seeing gains in termsof power and performance and
especially when we move from onetransistor architecture to the
next.
For example, we will be verysoon adopting gate all-around
technology.
Intel calls it ribbon-fed.
(14:00):
The transistor itself will giveyou better performance, better
power performance, but you won'tnecessarily shrink the
footprint of the transistorcompared to its fin-fed
equivalent.
So there are benefits to movingat least some portion of your
design to these very advancednodes.
But then at the same time werealize when you have a logic
(14:20):
design you need to have SRAMwith it.
Now SRAM hasn't really scaledsince 5 nanometer.
We actually see a growth.
It's actually reverse scalingif you compare 3 nanometer SRAM
with the 5 nanometer SRAM.
When you look at the cost perbit of an SRAM cell, it actually
it's been a while.
I think 7 nanometer probablywas the last node, was the
cheapest node and since then wehave been paying more per bit of
(14:43):
SRAM in our dyes.
So you're forced to dodesegregation of the dye.
Now that's where the advancedpackaging becomes very important
, especially 3D stack, becausewhat is happening is because
when you chop a dye into two andput it in the same package, now
the package is bigger, itsfootprint on the PCB is bigger.
So there are a lot of systemsthat are space constrained, like
(15:05):
a mobile phone.
You have only so much of X, yand Z available to you, and
that's why 3D becomesinteresting.
3d also becomes interestingbecause, when you put things
vertically, the length of theroute between those two chiplets
are very, very small,non-existent in some cases.
They are directly connectedthrough the bump short, micro
bump short or the hybrid bumpshort, so you get a lot more
(15:28):
electrical performance out ofthe design.
Through this stack, also, youare gaining on the footprint.
The challenge, though, isyou're folding the design onto
itself.
So, for a two-stack 3D, yourpower is doubling, your density
is doubling, so you have thermalchallenge combined with power
challenge combined with signalintegrity challenges, right?
(15:48):
So all of that has to beanalyzed in tandem for 3D IC,
which in the past we didn't doso much.
Francoise von Trapp (15:53):
EDA is really critical to this.
Pratyush Kamal (15:56):
EDA is very critical to this.
Yes, yeah.
Francoise von Trapp (15:59):
How has the chip designers world changed
, as Moore's law has slowed?
Pratyush Kamal (16:03):
Before we go there, I want to tell you that
the way this whole capitalindustrial base works, right.
Okay, you build a perfectlyfunctioning iPhone X and it has
four-year longevity.
But both from the supplier'sperspective as well as from the
customer's perspective, there isan expectation built in that we
will be upscaling the productevery so many years.
(16:27):
Right?
Every year we want to add morefunctions and we want to make
things cheaper at the same time.
But what is happening is, withthe slowdown of Moore's law,
companies can't quite addfunctions anymore without
exploding the cost of theirdesigns.
So suddenly there has been alot of emphasis and that is
(16:50):
again coming from my ownpersonal experience on squeezing
everything out of your design.
So in the past, because youhave a one year cadence to do
the design and get it out thedoor, get it manufactured, get
it tested.
To do the design and get it outthe door, get it manufactured,
get it tested, you would leave alot on the table.
As long as the design isimplemented fully functionally,
you are okay.
It didn't matter whether weleave 5% or 10% of area or power
(17:16):
on the table.
We didn't fully squeeze thatout.
It was okay.
The cadence was more important.
But as things slow down,certainly there is more
opportunity now for designers tosqueeze more out.
So there's a lot of emphasis onoptimization and it has the
moment.
Designers now understand theneed and the economic benefit of
optimization tangible benefitof optimization suddenly
(17:37):
co-design becomes a palatableoption for them, right.
So so fundamentally, people aregetting open to the idea of
using cross-functional tools.
If I'm a silicon designer, I'mgetting more interested in how
the package works.
Can I save something in siliconthrough some clever
implementation within thepackage?
Francoise von Trapp (17:57):
And there wasn't that awareness before.
Pratyush Kamal (17:59):
It wasn't that awareness, because we were doing
free scaling, we were gettingcheap scaling, so we didn't need
to.
Francoise von Trapp (18:07):
But there's also different drivers.
Now.
It's not just the smartphonechips, right, it's also.
We're talking abouthigh-performance computing and
data centers and all of theseplaces where, like the AI, chips
, are really what's driving theindustry.
How are the end devicesimpacting at the EDA level?
Pratyush Kamal (18:25):
So definitely the scale is the first concern
when you look at the datacenter-based applications, and
the scale doesn't stop at thechip or the package boundary
anymore or the rack itself.
Right, it's rack to rack.
We are talking about datacenter to data center
communication as well.
The systems of yesterday werebounded.
There were limited size systemsversus with cloud as part of
(18:50):
our computation platformeverywhere, I see our system as
limitless.
It's like the universe.
There's no end to it.
So the solution you put inthere today you have to think of
it in terms of scalability.
All the data center applicationsare leveraging advanced
packaging.
It's ushering in newinnovations within the package
(19:10):
and outside of package as well.
A lot of this communication isalso employing optical
communication.
So optics is becoming verytightly integrated with silicon
today.
So you hear a lot about theco-package optics.
So when we do an electricalsimulation, we have to think
about the optical domain as welland vice versa.
(19:31):
And just staying with theconventional chips.
Also because 3D IC doubles yourpower density and that directly
impacts your thermal.
We have been thermally limitedin all our systems, whether it's
the data center, whether it'sthe mobile phone, more so in the
mobile phone than in datacenter because we have better
thermal mitigation options there.
(19:52):
But 3D IC doubles thatchallenge or triples, based on
the number of stack that youhave, quadruples it there.
So you have to be able to donot just the thermal simulation
by itself but thermal a raredesign right.
When you're designing upfrontyou have to think about thermal
very early on.
Or when you're doing yourthermal you have to understand
(20:14):
what is the effect on stress dueto it or what is the effect of
thermal on the electricalperformance of the transistor.
You have to do these thingsmore closely Now.
In the past, when we had asingle design, we would look at
the worst case thermal, do astatic analysis and as long as
it's meeting the thermalboundary condition specs, we are
(20:35):
fine.
But today, what is happening?
When you do two dye or more intandem design, there will be
thermal coupling between themand as you are doing different
design, there could be heatresonance because one dye is
wasted, heat is flowing throughthe other dye, so there could be
resonance phenomena occurringin there and we don't understand
any of that.
We have never simulated that inthe past.
(20:56):
So that's why the need formultiphysics, dynamic simulation
comes in, so the need forcomputation.
When you're doing thesecomputations, you need a lot
more computational resourcesthan you have in the past.
So it's really redefining theADA space, because we can't just
keep throwing more and moremachines to get a bigger job
(21:18):
done.
And that's where AI comes intoplay.
Ai is helping us make oursimulation runs efficient.
Ai is helping us make oursimulation runs more
user-friendly.
We one day hope to see a worldwhere, as an end user I'm an
electrical engineer I'm able torun a mechanical simulation with
the help of AI.
(21:38):
It teaches me enough for me tounderstand what to do and to
read the results.
Francoise von Trapp (21:44):
For a chip designer who has to think about
not just the chips anymore, buthow it's going to perform in
the package and what the packageis going to do to that chip.
Is it the job of the EDAsoftware tools to provide that
information back?
If you make this adjustment inyour design, this is what it's
going to look like at the endand feed that information back
(22:06):
so they can adjust thataccordingly.
Pratyush Kamal (22:09):
Yeah, All of the EDA vendors want to do that,
are doing that.
Francoise von Trapp (22:18):
What we are trying to do now different
is we want to do it more upfront.
Pratyush Kamal (22:23):
Right, right, okay, because the earlier you
design these things in, thefewer problems you have down the
road.
Yeah, and 3D is very expensive,so you want to catch it even
earlier than you did in 3D.
Francoise von Trapp (22:28):
Well, and that seems to be one of the
motivations all the way aroundis that we've accepted the fact
that this is a costly endeavor.
And so how do we mitigate costs?
You know, by improving theyields, by having the design
determined way up front, all theway through the system.
So for a designer of tools, forinstance, you will have a
background in chip design, butnow you're working at an EDA
(22:48):
company and you're relying onthat experience you have from a
design perspective to helpdevelop the next tools, knowing
what you, as a designer, needfrom an EDA tool right.
Pratyush Kamal (22:59):
That's correct.
Francoise von Trapp (22:59):
And it used to be.
For instance, when I'd go toconferences, I would notice that
you'd be at an advancedpackaging conference and there
wouldn't be any design companiesthere.
They were at their ownconferences, like you know DAC
or DesignCon or whatever.
But now you see there is all ofthe design houses are actually
having a presence at conferences, speaking at conferences.
(23:23):
There's design tool tracks now.
So what do you, as an EDAcompany, need to know from the
advanced packaging community?
What kind of things do you needfrom them to succeed in
developing the tools that theyneed?
Pratyush Kamal (23:38):
At the very basic.
We need to understand theunderlying package technology
that the chip will employ andthat will translate to what kind
of interfaces we can put on thechip to connect them together.
It will also define what kindof boundary conditions we'll see
in terms of thermal, what otherchallenges we'll see.
So the package, the choice ofthe material, the choice of
(24:00):
interconnect technology withinthe package are very critical,
and these are the two componentsreally within the package.
But it's not just about thepackage by itself.
Package is being used toconnect two chips now two
chiplets, so you need more ormore, yeah or more, and
different functionalitiesdifferent functionalities.
Francoise von Trapp (24:21):
You were talking about s ram before we
also have other right like rfdevices and all of that right
yeah, analog and logic yeah inthe past.
Pratyush Kamal (24:30):
When you look at a pcb, you have so many chips
on the pcb and they talk to eachother, right, but the
communication is very slowbecause each chip is designed to
work on its own.
Of course, every chip requiressome input data and that it uses
to provide you with some outputdata.
But all of that interface?
Today on the pcb, everything isvery structured, defined, there
(24:51):
is a stack defined for it.
But conversion of language fromone stack to the other through
the stack takes time, takeslatency, takes area, takes power
.
When you put two chiplets intoa package, you're trying to
minimize that cost.
That's the whole idea ofputting things closer together.
So now you have suddenlyimproved your data latency, you
(25:12):
have improved your data powerefficiency.
You have suddenly improved yourdata latency.
You have improved your datapower efficiency, you have
improved your data throughput.
But that's not enough.
You need to design them also intandem together, because these
chiplet by definition.
You want to leverage resourcesfrom each other, right?
So take the example of on-chipnon-volatile memory.
Why duplicate it across bothchips when you can make do with
(25:34):
one chiplet?
Because it's expensive to addthose flavors on a chiplet, and
especially when we look at wherethe industry is headed.
If you look at the UCI 2.0 spec, it talks about
interoperability.
The whole 2.0 spec is reallybuilt with that in mind.
How do we enable open chipletecosystem?
We are not just stopping atdesigning two chiplets together.
(25:55):
We want to design a chiplet oftomorrow that can work with any
chiplet from any third-partyvendor as well.
Francoise von Trapp (26:02):
Yeah, that's why we have the UCIE
right, the common interface, andthere's a couple others.
I think there's a bunch ofwires is the other one.
Pratyush Kamal (26:09):
Bunch of wires is the other one.
Ucie is the one getting themost traction currently because
it really serves the need ofhigh-performance computer
applications out the door.
As it was defined in 1.0 spec,they come with a lot of flavors.
There are a lot of optionalfeatures.
I think that the UCI may alsobecome a tiered interface where
(26:30):
you will have different layerlevel of certification.
Francoise von Trapp (26:33):
So just telling that I have a ucie
compliance chip alone would notbe enough for tomorrow you'll
have to probably categorize whatkind of ucie are you using,
because of all the configurationflexibility you have there so I
want to switch gears just atiny bit to talk about one of my
hot button items right now,which is the amount of power AI
(26:55):
uses in training large languagemodels and the stress that's
going to be putting on the grid.
Isn't there a role for EDA toplay in helping to reduce that
massive energy appetite of AI?
Pratyush Kamal (27:12):
Definitely.
We had a role to play yesterday.
We will have continued role toplay.
The more power becomes aproblem, the bigger role we'll
have, because every person thatwe save off a larger footprint
is a massive saving in itself.
We all saw Google's ex-CEO,eric Schmidt, recently made a
statement that by 2030, hemisspoke 99%, but it was
(27:33):
actually 9.9% or something.
So basically, usa's totalenergy consumption.
Francoise von Trapp (27:39):
Wait, he misspoke, it's not 99%.
Pratyush Kamal (27:41):
No, it's not.
Francoise von Trapp (27:42):
It's going all over the place.
Pratyush Kamal (27:44):
Yeah, it became a meme because the numbers he
used they don't line up to 99.
I was like 99 doesn't soundcorrect, that's huge.
There's a big difference.
It became a meme.
Yeah, I know it's becausethey're still talking about tens
of gigawatts, they're nottalking about terawatt right If
you look at the whole.
US, as a country we are interawatt probably, range EDA is
(28:05):
becoming more and more criticalto solving the data center power
problem.
First thing, first till now,when we design chips for data
center applications, power wasnot our constraint.
Thermal was our constraint ourability to draw thermal.
Right right right Now they'revery tightly coupled.
More power means more thermal,so indirectly you were
(28:27):
addressing power, but that wasnot the design constraint you
gave to your chip.
You gave a thermal constraintto your chip and a lot of early
data center adapters benefited alot from subsidized electricity
.
All over the world the need fordata center is changing.
We are talking about 10% of USelectricity consumption will be
in data centers by 2030.
That's a big number.
(28:48):
We are basing it based on theneed of what we think the AI
hardware need will evolve in thenext five years, but things
could accelerate beyond ourcomprehension because we are
allowing the machines to makedecisions for us.
They're getting smarter by day,so there's an exponential
snowball effect that, in termsof design complexity that may
very soon arise, complexity thatmay very soon arise Once we
(29:16):
have, let's say, learned toharness AI in terms of chip
design, we won't stop at atrillion transistor design.
We will aim to put the wholeend-to-end system as a single
entity.
Francoise von Trapp (29:23):
So when you talk about thermal, though
you know, one of the things I'velearned recently is that heat
equals energy loss.
Pratyush Kamal (29:31):
Yeah.
Francoise von Trapp (29:32):
If you can reduce the energy loss, then it
also impacts how much heat'sbeing put out.
Right, if you're, if you'remaking things more energy
efficient, then it's going toimpact that thermal footprint
and reduce the amount of powerthat's actually used, because
you're keeping all of thatenergy in use.
It's not, you're not justexpending it.
(29:53):
Yeah, yeah, is that right?
Did I say that right?
Pratyush Kamal (29:56):
That's right, yeah.
The other reason suddenly theenergy consumption in data
centers became a centerpiece isbecause AI data centers in the
last few generations startedadopting desegregated designs.
The designs became so big theystarted desegregating, so there
was an added cost of cutting amonolithic die into two as well
(30:19):
there.
So I just wanted to add that aswell.
Francoise von Trapp (30:24):
With chiplets, we are disaggregating
right.
Pratyush Kamal (30:28):
Yeah.
Francoise von Trapp (30:29):
But we're also re-aggregating into one
device and putting everything asclose as possible to make them
more efficient.
Pratyush Kamal (30:37):
Yeah.
Francoise von Trapp (30:38):
So chiplets are also a push towards
that efficiency for AI.
Pratyush Kamal (30:43):
Yeah, yeah, individual chiplets are becoming
more efficient by themselves,but you have the added overhead
of connecting the two and youburn extra power there.
Francoise von Trapp (30:52):
Okay, so we've been talking a lot about
how important the EDA industryis to semiconductor
manufacturing.
What role does Siemens play inproviding 3D IC design tools to
the industry?
Pratyush Kamal (31:07):
Siemens is playing a very central role.
We are one of the three largeorganizations that have a whole
suite of tools to realize your3D design from concept to tape
out.
What we are doing currently istaking all of our silicon tools,
all of our packaging tools, andwe are not stopping there.
We are looking at ourmechanical design tools, for
(31:27):
example, computational fluiddynamics.
We are bringing all of theseunder a single umbrella.
We are trying to see how we canstitch them together, how we
can automate the data exchangeacross different tools by
standardizing the language theyspeak, the information that
needs to be passed on to a tool.
For example, we are veryfamiliar with the concept of
(31:48):
design kits in the silicon world.
Foundries provide the designkit and it becomes as a Lego
piece to you and then you justput those Lego pieces together
and build your chip.
In the silicon world we did notfollow that practice in
packaging till now.
Siemens is leading the efforthere across the industry is
trying to standardize thatlanguage.
We don't want to read aPDF-based design rule manual and
(32:11):
build a chip based on that.
We want to automate thatlanguage.
We want our tools one tool tounderstand the language of
another tool, whether it's fromSiemens or from Cadence or from
Synopsys.
So we are trying to makeinteroperability as a very
central to our 3D IC workflows.
We are creating loops betweendifferent tools and different
(32:32):
workflows.
What I mean by a workflow isbasically a physical design.
Workflow is essentiallyeverything relating to
physically designing that entity, whether it's a floor planning
of the chip, floor planning ofthe package.
How do you do the bumpconnections, how do you do the
interposer or the substraterouting.
It's all part of the physicaldesign workflow.
(32:53):
It doesn't stop there.
Nothing is done until youverify it.
So, of course, verification isalso part of that workflow.
So that's what I mean.
So we are trying to createthese workflows and stitch them
together as well, Because whenyou are doing a physical design,
you need to know thermal, youneed to know your signal
integrity implications.
Power is always at the centerof 3D ICs.
(33:16):
I can't put the emphasisanymore on it.
Francoise von Trapp (33:20):
To wrap things up, can you summarize
what you would want listeners totake away from this
conversation?
Maybe the three top points thatyou want to make here.
Pratyush Kamal (33:31):
I can promise my customers that, as a
representative of the EDAindustry, we understand your
challenge as well as you do.
We understand your complexityand that's why, philosophically,
the EDA industry is starting tosee the need for a
solution-focused software thanan isolated software by itself.
(33:52):
The software by itself meansnothing until it gives you a
solution right.
So we are also trying to enablean open-chiplet economy as an
EDA industry representative, andthat will allow our customers
flexibility to use best-in-classtools.
(34:13):
They won't be forced orobligated to use tools that they
don't want to, but becausethey're part of that workflow
today, they are forced to usecertain tools.
So we want to allow our usersthat flexibility tomorrow.
And the third thing is, with AIavailable as a tool to us, we
expect a future where our userswill be able to work at a higher
(34:37):
level of abstraction andbecause the workforce of
tomorrow that we see is going tobe consisting of experts with a
very deep vertical domain focus, but more of a broad focus.
And the last thing is what weunderstand is in the United
(34:57):
States, the average age of adouble E is 57.
We need a lot, many moreengineers to be able to do the
work and, as you can see, it'sreally dominated by people who
are very close to retiring, sowe'll have even more labor
challenge in future.
So EDA industry, because that'swhere the design starts.
So we are very focused onbuilding workforce of tomorrow
(35:21):
and we work very closely withthe universities in terms of
providing them educationalsoftware and training the next
generation of engineers andcreating excitement around EDA,
3d, ic and advanced packaging.
Francoise von Trapp (35:35):
So if they're learning to be a chip
package designer in school rightnow, they could possibly be
using the tools or learning onthe tools that they're going to
be using in the field.
Yeah, okay, all right.
Well, where can people go tolearn more?
Pratyush Kamal (35:50):
Please visit us at wwwsiemenscom and you will
learn about all the excitingtechnologies that we have for
you to build your nextgeneration chip.
Francoise von Trapp (36:00):
Okay, great.
Thank you so much, Pariyush.
Pratyush Kamal (36:03):
You're welcome.
Thank you, Frances.
Francoise von Trapp (36:09):
To explore how Siemens is shaping the
future of 3DIC design, head overto siemenscom slash 3DIC and
see how you can bring your nextgeneration chip designs to life.
And if you're listening priorto June 22nd and will be
attending DAC, make sure tovisit the Siemens booth on the
exhibitor floor.
There's lots more to come, sotune in next time to the 3D
Insights podcast.
(36:30):
The 3D Insights podcast is aproduction of 3D Insights LLC.
Looking to stay ahead in the chiplet
revolution.
With 3DICs transformingeverything from AI to mobile and
data center design, Siemens EDAis making it easier than ever
to manage complexity andaccelerate innovation.
Their comprehensive 3DICsolution brings together
architecture, exploration,thermal analysis, verification
and co-design all in one unifiedplatform.
(00:24):
If you're navigating multi-diesystems, this is the competitive
edge you've been waiting for.
Visit siemenscom slash 3DIC tolearn more.
Hi there, I'm Francoise vonTrapp, and this is the 3D
(00:45):
Insights Podcast.
Hi everyone, you know if we'veheard it once, we've heard it a
hundred times on this podcast.
3dic using advanced packagingtechnologies are critical to
achieving power, performancearea and cost of next generation
semiconductor devices, and itreally looks like that next
(01:08):
generation that we've beentalking about for so long is
actually here.
It's now.
Design engineers know it andthey need the support of the EDA
or the electronic designautomation segment of the
industry.
So here to talk to me aboutthis important topic is Pratyush
Kamal.
He's the 3D IC expert, whohappens to work at Siemens
Digital Industries Software.
(01:30):
Welcome to the podcast,Pratyush.
Pratyush Kamal (01:32):
Thank you, Francoise, for having me here.
Francoise von Trapp (01:35):
So, before we dive in, can you tell me a
little bit about your backgroundand your current role at
Siemens and previous roles thatbrought you to this point?
Pratyush Kamal (01:44):
Sure, Francoise.
So I joined Siemens roughly twoyears ago.
I joined as a contractor,helping Siemens on their
government engagements,especially DARPA-driven projects
, and then for the last one yearI've been a full-time employee
and in my current role I'm theDirector of Central Engineering
Solutions and our charter isreally to look at a holistic
(02:04):
solution for 3D ICs as well asanything any new technologies
that is evolving when we talkabout two nanometer and below
nodes, because they really aretied to, as far as the usage
goes, advanced packaging in someform or the other very
intricately.
So that's the focus of ourcurrent organization.
It's a new team that has beenput together and we have a lot
(02:26):
of subject matter experts,people with different design
domain expertise, and I'm,overall, the technical lead for
this organization.
And prior to joining Siemens, Ihad many, many years of
experience.
I started my career as a designengineer, Then I grappled with
EDA industry for a while.
Engineer, then I grappled withEDA industry for a while and
(02:48):
then I spent 15 plus yearsdesigning chips and also
defining architecture for thechips as well as the systems.
I spent a lot of my career atQualcomm, a bit at Google as
well.
It's at Qualcomm, 10 plus yearsago that I first got introduced
to 3D IC and at the time wewere trying to look at a
long-term view of 3DIC howeventually, you know, when we
look at CFET and stacktechnologies of the future.
(03:09):
We were thinking about it 10years ago, but we realized the
challenges that lay ahead, so weshifted our focus on
stacked-based 3DIC, and a greatexample of that is a hybrid
bond-based wafer-on-wafer orchip-on-wafer stack.
So we picked that as ourresearch vehicle, but it didn't
prevent us from looking at other3D stack-based integration
(03:30):
options.
Francoise von Trapp (03:31):
So you know, when I first got into this
industry in 2005, I've alwaysfound the design side of things
to be very hard for me to grasp.
I have an easier time with thephysical, you know, and seeing
how things are structured.
And I remember talking to someof the experts when Siemens was
mentor and they were juststarting to look at co-design
(03:54):
and co-design optimization andthis is 20 years ago.
And how has that conversationchanged?
What kind of brought thatrealization that now it's all
this time and you're justdeveloping this actual team to
focus on that in the 3DIC space?
But can you explain a littlebit how that evolution occurred?
Pratyush Kamal (04:16):
The way I look at it, it almost seems like we
put this industry as anafterthought.
We first discovered thetransistor.
We manually learned to lay thattransistor.
All the words we continue touse today, they are all related
to manual processes, for example, tape out.
There was an actual tape thatwas involved in the tape out.
So we did everything manual.
(04:37):
And then one day some of usthought, okay, let's actually
try to automate that.
Then we built some tools.
We started putting more andmore complex circuits together.
As long as we were dealing withhundreds of thousands, the need
for automation was still small.
But the moment we shifted totrue VLSI, very large scale
integration, where you'redealing with millions and
millions, and today we arelooking at trillion transistor
(04:59):
designs Then we realized wecan't do everything manually and
over the years the industrydrove itself to automation.
That evolution happened.
But again, if you look at thewhole chip design process, it's
very complex.
It requires expertise from somany different fields.
Just the definition of atransistor requires multiple
expertise, right, and the amountof analysis the software needed
(05:20):
to do that is very diverse innature, and so that's one reason
why the way the EDA industrytoday is.
The design flows are veryfragmented.
For the many years now we havetalked about RTL to GDS,
holistic flows, and if you lookat the big EDA organizations,
they all have competingsolutions in the whole domain,
starting all the way from yourabstract definition of your
(05:43):
system, whether it's System C orwhatever, and bringing it all
the way down to the GDS that yousend to the foundry.
Right, this whole RTL to GDS, infact it's not even RTL, it's
behavioral to GDS.
Now we are talking, right,there are so many different
pieces of software involved hereand they have to be stitched
together over the years, formingwhat I call a patchwork,
(06:03):
quilted approach to designautomation.
So, yeah, it has been a lot ofover-the-wall approach because,
again, the expertise is sodiverse through this whole
process.
But as the complexitiesincrease and as new tools become
available to us tools likeartificial intelligence, that's
the case in point here we canstart to bring some of these
(06:24):
boundaries down, walls down.
We can start to imagineourselves as cross-functional
experts, even though we don'thave that background.
But we have these tools at ourdisposal today that will
tomorrow allow us to me, as anelectrical engineer, can
tomorrow dream to do mechanicalsimulations.
So that's what we are trying todo in 3D IC of today across the
(06:45):
industry.
Francoise von Trapp (06:46):
So you're saying what drove this is the
need for developing these inhigher volumes.
The devices are now in such avolume that it can't be done
manually.
But what if, when they startedthinking about not just chip
design and designing reallycomplex chips, but when they
started realizing that you notonly had to think about the chip
(07:09):
, you also had to think aboutthe package and the system and
maybe work it all the way backso that what you're designing in
a chip was going to be able tobe carried through?
Pratyush Kamal (07:20):
Yeah, I mean until very recently, if we take
the very high performancecompute market out, because it's
always spearheading in terms ofneeds by very definition.
But my previous experience wasin the mobile space and I'll
tell you anecdotally, as asilicon designer, we never
thought about the package.
It was an afterthought.
We designed our GDS, we threwit over the wall and then
(07:40):
somebody put a mold around itand it worked.
Right right and then somebodyput a mold around it and it
worked Right.
Right, as we started tothrottle up our speeds,
interface speeds, as our powerdensities increased, we started
to see challenges.
So then I mean, even today,most of the package design is
done in Windows environment.
Roughly 10 years ago was thefirst time I actually opened a
package layout in an EDA tool.
(08:02):
I wouldn't name the EDA toolinvolved there, but for the
first time I actually botheredto look at a layout, and the
reason for it was because I wasthe interface architect and we
had SI challenges on thatinterface and it was not a very
high speed interface.
We were talking PCIe 3.0 here,very small compared to PCIe 6.0
that we are starting to see.
(08:23):
You know, at least in thespecification space we are
discussing those.
What caught me by surprise wasthat it was actually a
Windows-based software.
I had never dealt with aWindows-based interface in
Silicon design world.
It came as a shock Then.
That's when I realized howdifferent package design and how
uncoupled it is from theSilicon world and how uncoupled
(08:45):
it is from the silicon world.
And today, as our team looks atco-design and looks at how we
can design these chiplets intandem because they will be used
in tandem in an advancedpackage tomorrow.
We have started to realize thegaps that exist.
You have to do a lot of dataconversion.
You have to not only do that,you have to move data across
different servers, differentfile formats and file servers.
(09:12):
So we are trying to bridge todecoupled world here through 3D
IC engagement Okay.
Francoise von Trapp (09:15):
So it's a very complex challenge to solve,
and so I can see where, earlyon, if you had manual that works
, if, until it was volume, therewas no need for EDA.
So it always seemed to me, likeyou know, you knew something
was approachingcommercialization if suddenly
there was an EDA tool for it.
Right In the beginning, when itwas still in R&D, until the EDA
(09:37):
tool came along, you knew thatsomething that was manufactured
in volumes.
But now everything's hopping ina little more close together.
We don't seem to be waiting aslong to engage the EDA vendors.
It seems to be more part of theholistic approach.
Is that true?
Pratyush Kamal (09:55):
That is true, and the reason for it again, is
the complexity of design.
What people realized is thatthe EDA industry evolves in
steps.
There'll be innovation and thenthere would be nothing for the
next few years, and thensomething new will come up.
Everybody will jump on thebandwagon and we will evolve,
and then the cadence is slow inthat sense.
Right the place and route tool.
Fundamentally, if you look atthe core algorithm, it hasn't
(10:18):
changed.
It has evolved.
The fundamental algorithm isstill the same as it was 25
years ago and you're very right.
Bang on on making thatassumption that when the EDA
tools appear, you have anindication of what is coming in
terms of actual end product.
I'll tell you a direct 3D ICanecdotal story that I have.
So I was part of QualcommResearch and we were working
(10:40):
with TSMC at the time, who wereusing hybrid band 3D-based 3D
stack for camera-basedapplications, image sensing
applications.
So we had an idea how we canexpand this to logic-on-logic 3D
application, make it completelygeneric, right?
So we built a couple of testchips.
We did not have any CAD toolsavailable to us, so we had to
(11:04):
hack everything ourselves and wespoke to a couple of EDA
companies at the time on behalfof Qualcomm and we did not get a
lot of collaboration becausethey wanted to first see whether
there was any product on theroadmap, whether there was a
path to commercialization forthis technology.
And we realized very soon thatwe don't have the budget to
spend tens of millions ofdollars just for tool
(11:27):
development when we have a fewthousands of dollars for the
product development as part ofthe R&D.
So we had to shelve our 3D ICFfor our ambitions 10 plus years
ago because of that limitation.
What has changed in the last 10years is A end of scaling On
paper.
We are still scaling things.
We are going from 5 to 4 to 3to 2 nanometer, but you're not
(11:48):
getting the same dimensionalshrink Plus.
You're not getting iteconomically.
You're actually paying more tobuild a smaller transistor,
unlike in the past.
Francoise von Trapp (11:58):
It seems like it's just being able to say
that we can do it.
It's not really about Moore'slaw anymore, it's that can we
keep scaling down, but then youalso have to look at packaging
that right.
Pratyush Kamal (12:09):
Yeah, I'll tell you why.
That packaging becomes verycritical for smaller technology
Because it's a very complexprocess.
The whole way for stackformation is much, much, much
more complex.
We are starting to use EUV.
Formation is much, much, muchmore complex.
We are starting to use UV.
We will be very shortly usinghigh-end UV-based solutions for
lithography.
The challenge is the industryhasn't yet fully understood the
(12:32):
defect mechanism through UV.
There is a lot of controlissues and we are talking about
22, 24 nanometer pitches here,and you can imagine the
stochastic challenges that wehave to deal with at that
geometry.
So what we are seeing is, eventhough we can yield designs in
these technology nodes, theyields are very poor, especially
(12:55):
as a dye size grows.
There is an exponentialcorrelation to the yield that
you'll get the larger the dye,the lower the yield.
So now, by definition, forthese technologies to be
economically feasible, you mustlimit your die size, otherwise
there'll be so many bad dies onyour wafer that it would not
make sense to you, and that'swhy the whole industry is moving
(13:19):
away from the idea of SOCsilicon on chip, where we talked
about a monolithic design whereall the functionality of the
system of the PCB goes insidethe die.
We are getting incrementalscaling advantage in these
technology nodes.
But there is other advantagethat drives the need for these
(13:39):
smaller to smaller nodesprimarily the performance and
power.
You may not be able to shrinkthe area as much, but you are
definitely seeing gains in termsof power and performance and
especially when we move from onetransistor architecture to the
next.
For example, we will be verysoon adopting gate all-around
technology.
Intel calls it ribbon-fed.
(14:00):
The transistor itself will giveyou better performance, better
power performance, but you won'tnecessarily shrink the
footprint of the transistorcompared to its fin-fed
equivalent.
So there are benefits to movingat least some portion of your
design to these very advancednodes.
But then at the same time werealize when you have a logic
(14:20):
design you need to have SRAMwith it.
Now SRAM hasn't really scaledsince 5 nanometer.
We actually see a growth.
It's actually reverse scalingif you compare 3 nanometer SRAM
with the 5 nanometer SRAM.
When you look at the cost perbit of an SRAM cell, it actually
it's been a while.
I think 7 nanometer probablywas the last node, was the
cheapest node and since then wehave been paying more per bit of
(14:43):
SRAM in our dyes.
So you're forced to dodesegregation of the dye.
Now that's where the advancedpackaging becomes very important
, especially 3D stack, becausewhat is happening is because
when you chop a dye into two andput it in the same package, now
the package is bigger, itsfootprint on the PCB is bigger.
So there are a lot of systemsthat are space constrained, like
(15:05):
a mobile phone.
You have only so much of X, yand Z available to you, and
that's why 3D becomesinteresting.
3d also becomes interestingbecause, when you put things
vertically, the length of theroute between those two chiplets
are very, very small,non-existent in some cases.
They are directly connectedthrough the bump short, micro
bump short or the hybrid bumpshort, so you get a lot more
(15:28):
electrical performance out ofthe design.
Through this stack, also, youare gaining on the footprint.
The challenge, though, isyou're folding the design onto
itself.
So, for a two-stack 3D, yourpower is doubling, your density
is doubling, so you have thermalchallenge combined with power
challenge combined with signalintegrity challenges, right?
(15:48):
So all of that has to beanalyzed in tandem for 3D IC,
which in the past we didn't doso much.
Francoise von Trapp (15:53):
EDA is really critical to this.
Pratyush Kamal (15:56):
EDA is very critical to this.
Yes, yeah.
Francoise von Trapp (15:59):
How has the chip designers world changed
, as Moore's law has slowed?
Pratyush Kamal (16:03):
Before we go there, I want to tell you that
the way this whole capitalindustrial base works, right.
Okay, you build a perfectlyfunctioning iPhone X and it has
four-year longevity.
But both from the supplier'sperspective as well as from the
customer's perspective, there isan expectation built in that we
will be upscaling the productevery so many years.
(16:27):
Right?
Every year we want to add morefunctions and we want to make
things cheaper at the same time.
But what is happening is, withthe slowdown of Moore's law,
companies can't quite addfunctions anymore without
exploding the cost of theirdesigns.
So suddenly there has been alot of emphasis and that is
(16:50):
again coming from my ownpersonal experience on squeezing
everything out of your design.
So in the past, because youhave a one year cadence to do
the design and get it out thedoor, get it manufactured, get
it tested.
To do the design and get it outthe door, get it manufactured,
get it tested, you would leave alot on the table.
As long as the design isimplemented fully functionally,
you are okay.
It didn't matter whether weleave 5% or 10% of area or power
(17:16):
on the table.
We didn't fully squeeze thatout.
It was okay.
The cadence was more important.
But as things slow down,certainly there is more
opportunity now for designers tosqueeze more out.
So there's a lot of emphasis onoptimization and it has the
moment.
Designers now understand theneed and the economic benefit of
optimization tangible benefitof optimization suddenly
(17:37):
co-design becomes a palatableoption for them, right.
So so fundamentally, people aregetting open to the idea of
using cross-functional tools.
If I'm a silicon designer, I'mgetting more interested in how
the package works.
Can I save something in siliconthrough some clever
implementation within thepackage?
Francoise von Trapp (17:57):
And there wasn't that awareness before.
Pratyush Kamal (17:59):
It wasn't that awareness, because we were doing
free scaling, we were gettingcheap scaling, so we didn't need
to.
Francoise von Trapp (18:07):
But there's also different drivers.
Now.
It's not just the smartphonechips, right, it's also.
We're talking abouthigh-performance computing and
data centers and all of theseplaces where, like the AI, chips
, are really what's driving theindustry.
How are the end devicesimpacting at the EDA level?
Pratyush Kamal (18:25):
So definitely the scale is the first concern
when you look at the datacenter-based applications, and
the scale doesn't stop at thechip or the package boundary
anymore or the rack itself.
Right, it's rack to rack.
We are talking about datacenter to data center
communication as well.
The systems of yesterday werebounded.
There were limited size systemsversus with cloud as part of
(18:50):
our computation platformeverywhere, I see our system as
limitless.
It's like the universe.
There's no end to it.
So the solution you put inthere today you have to think of
it in terms of scalability.
All the data center applicationsare leveraging advanced
packaging.
It's ushering in newinnovations within the package
(19:10):
and outside of package as well.
A lot of this communication isalso employing optical
communication.
So optics is becoming verytightly integrated with silicon
today.
So you hear a lot about theco-package optics.
So when we do an electricalsimulation, we have to think
about the optical domain as welland vice versa.
(19:31):
And just staying with theconventional chips.
Also because 3D IC doubles yourpower density and that directly
impacts your thermal.
We have been thermally limitedin all our systems, whether it's
the data center, whether it'sthe mobile phone, more so in the
mobile phone than in datacenter because we have better
thermal mitigation options there.
(19:52):
But 3D IC doubles thatchallenge or triples, based on
the number of stack that youhave, quadruples it there.
So you have to be able to donot just the thermal simulation
by itself but thermal a raredesign right.
When you're designing upfrontyou have to think about thermal
very early on.
Or when you're doing yourthermal you have to understand
(20:14):
what is the effect on stress dueto it or what is the effect of
thermal on the electricalperformance of the transistor.
You have to do these thingsmore closely Now.
In the past, when we had asingle design, we would look at
the worst case thermal, do astatic analysis and as long as
it's meeting the thermalboundary condition specs, we are
(20:35):
fine.
But today, what is happening?
When you do two dye or more intandem design, there will be
thermal coupling between themand as you are doing different
design, there could be heatresonance because one dye is
wasted, heat is flowing throughthe other dye, so there could be
resonance phenomena occurringin there and we don't understand
any of that.
We have never simulated that inthe past.
(20:56):
So that's why the need formultiphysics, dynamic simulation
comes in, so the need forcomputation.
When you're doing thesecomputations, you need a lot
more computational resourcesthan you have in the past.
So it's really redefining theADA space, because we can't just
keep throwing more and moremachines to get a bigger job
(21:18):
done.
And that's where AI comes intoplay.
Ai is helping us make oursimulation runs efficient.
Ai is helping us make oursimulation runs more
user-friendly.
We one day hope to see a worldwhere, as an end user I'm an
electrical engineer I'm able torun a mechanical simulation with
the help of AI.
(21:38):
It teaches me enough for me tounderstand what to do and to
read the results.
Francoise von Trapp (21:44):
For a chip designer who has to think about
not just the chips anymore, buthow it's going to perform in
the package and what the packageis going to do to that chip.
Is it the job of the EDAsoftware tools to provide that
information back?
If you make this adjustment inyour design, this is what it's
going to look like at the endand feed that information back
(22:06):
so they can adjust thataccordingly.
Pratyush Kamal (22:09):
Yeah, All of the EDA vendors want to do that,
are doing that.
Francoise von Trapp (22:18):
What we are trying to do now different
is we want to do it more upfront.
Pratyush Kamal (22:23):
Right, right, okay, because the earlier you
design these things in, thefewer problems you have down the
road.
Yeah, and 3D is very expensive,so you want to catch it even
earlier than you did in 3D.
Francoise von Trapp (22:28):
Well, and that seems to be one of the
motivations all the way aroundis that we've accepted the fact
that this is a costly endeavor.
And so how do we mitigate costs?
You know, by improving theyields, by having the design
determined way up front, all theway through the system.
So for a designer of tools, forinstance, you will have a
background in chip design, butnow you're working at an EDA
(22:48):
company and you're relying onthat experience you have from a
design perspective to helpdevelop the next tools, knowing
what you, as a designer, needfrom an EDA tool right.
Pratyush Kamal (22:59):
That's correct.
Francoise von Trapp (22:59):
And it used to be.
For instance, when I'd go toconferences, I would notice that
you'd be at an advancedpackaging conference and there
wouldn't be any design companiesthere.
They were at their ownconferences, like you know DAC
or DesignCon or whatever.
But now you see there is all ofthe design houses are actually
having a presence at conferences, speaking at conferences.
(23:23):
There's design tool tracks now.
So what do you, as an EDAcompany, need to know from the
advanced packaging community?
What kind of things do you needfrom them to succeed in
developing the tools that theyneed?
Pratyush Kamal (23:38):
At the very basic.
We need to understand theunderlying package technology
that the chip will employ andthat will translate to what kind
of interfaces we can put on thechip to connect them together.
It will also define what kindof boundary conditions we'll see
in terms of thermal, what otherchallenges we'll see.
So the package, the choice ofthe material, the choice of
(24:00):
interconnect technology withinthe package are very critical,
and these are the two componentsreally within the package.
But it's not just about thepackage by itself.
Package is being used toconnect two chips now two
chiplets, so you need more ormore, yeah or more, and
different functionalitiesdifferent functionalities.
Francoise von Trapp (24:21):
You were talking about s ram before we
also have other right like rfdevices and all of that right
yeah, analog and logic yeah inthe past.
Pratyush Kamal (24:30):
When you look at a pcb, you have so many chips
on the pcb and they talk to eachother, right, but the
communication is very slowbecause each chip is designed to
work on its own.
Of course, every chip requiressome input data and that it uses
to provide you with some outputdata.
But all of that interface?
Today on the pcb, everything isvery structured, defined, there
(24:51):
is a stack defined for it.
But conversion of language fromone stack to the other through
the stack takes time, takeslatency, takes area, takes power
.
When you put two chiplets intoa package, you're trying to
minimize that cost.
That's the whole idea ofputting things closer together.
So now you have suddenlyimproved your data latency, you
(25:12):
have improved your data powerefficiency.
You have suddenly improved yourdata latency.
You have improved your datapower efficiency, you have
improved your data throughput.
But that's not enough.
You need to design them also intandem together, because these
chiplet by definition.
You want to leverage resourcesfrom each other, right?
So take the example of on-chipnon-volatile memory.
Why duplicate it across bothchips when you can make do with
(25:34):
one chiplet?
Because it's expensive to addthose flavors on a chiplet, and
especially when we look at wherethe industry is headed.
If you look at the UCI 2.0 spec, it talks about
interoperability.
The whole 2.0 spec is reallybuilt with that in mind.
How do we enable open chipletecosystem?
We are not just stopping atdesigning two chiplets together.
(25:55):
We want to design a chiplet oftomorrow that can work with any
chiplet from any third-partyvendor as well.
Francoise von Trapp (26:02):
Yeah, that's why we have the UCIE
right, the common interface, andthere's a couple others.
I think there's a bunch ofwires is the other one.
Pratyush Kamal (26:09):
Bunch of wires is the other one.
Ucie is the one getting themost traction currently because
it really serves the need ofhigh-performance computer
applications out the door.
As it was defined in 1.0 spec,they come with a lot of flavors.
There are a lot of optionalfeatures.
I think that the UCI may alsobecome a tiered interface where
(26:30):
you will have different layerlevel of certification.
Francoise von Trapp (26:33):
So just telling that I have a ucie
compliance chip alone would notbe enough for tomorrow you'll
have to probably categorize whatkind of ucie are you using,
because of all the configurationflexibility you have there so I
want to switch gears just atiny bit to talk about one of my
hot button items right now,which is the amount of power AI
(26:55):
uses in training large languagemodels and the stress that's
going to be putting on the grid.
Isn't there a role for EDA toplay in helping to reduce that
massive energy appetite of AI?
Pratyush Kamal (27:12):
Definitely.
We had a role to play yesterday.
We will have continued role toplay.
The more power becomes aproblem, the bigger role we'll
have, because every person thatwe save off a larger footprint
is a massive saving in itself.
We all saw Google's ex-CEO,eric Schmidt, recently made a
statement that by 2030, hemisspoke 99%, but it was
(27:33):
actually 9.9% or something.
So basically, usa's totalenergy consumption.
Francoise von Trapp (27:39):
Wait, he misspoke, it's not 99%.
Pratyush Kamal (27:41):
No, it's not.
Francoise von Trapp (27:42):
It's going all over the place.
Pratyush Kamal (27:44):
Yeah, it became a meme because the numbers he
used they don't line up to 99.
I was like 99 doesn't soundcorrect, that's huge.
There's a big difference.
It became a meme.
Yeah, I know it's becausethey're still talking about tens
of gigawatts, they're nottalking about terawatt right If
you look at the whole.
US, as a country we are interawatt probably, range EDA is
(28:05):
becoming more and more criticalto solving the data center power
problem.
First thing, first till now,when we design chips for data
center applications, power wasnot our constraint.
Thermal was our constraint ourability to draw thermal.
Right right right Now they'revery tightly coupled.
More power means more thermal,so indirectly you were
(28:27):
addressing power, but that wasnot the design constraint you
gave to your chip.
You gave a thermal constraintto your chip and a lot of early
data center adapters benefited alot from subsidized electricity
.
All over the world the need fordata center is changing.
We are talking about 10% of USelectricity consumption will be
in data centers by 2030.
That's a big number.
(28:48):
We are basing it based on theneed of what we think the AI
hardware need will evolve in thenext five years, but things
could accelerate beyond ourcomprehension because we are
allowing the machines to makedecisions for us.
They're getting smarter by day,so there's an exponential
snowball effect that, in termsof design complexity that may
very soon arise, complexity thatmay very soon arise Once we
(29:16):
have, let's say, learned toharness AI in terms of chip
design, we won't stop at atrillion transistor design.
We will aim to put the wholeend-to-end system as a single
entity.
Francoise von Trapp (29:23):
So when you talk about thermal, though
you know, one of the things I'velearned recently is that heat
equals energy loss.
Pratyush Kamal (29:31):
Yeah.
Francoise von Trapp (29:32):
If you can reduce the energy loss, then it
also impacts how much heat'sbeing put out.
Right, if you're, if you'remaking things more energy
efficient, then it's going toimpact that thermal footprint
and reduce the amount of powerthat's actually used, because
you're keeping all of thatenergy in use.
It's not, you're not justexpending it.
(29:53):
Yeah, yeah, is that right?
Did I say that right?
Pratyush Kamal (29:56):
That's right, yeah.
The other reason suddenly theenergy consumption in data
centers became a centerpiece isbecause AI data centers in the
last few generations startedadopting desegregated designs.
The designs became so big theystarted desegregating, so there
was an added cost of cutting amonolithic die into two as well
(30:19):
there.
So I just wanted to add that aswell.
Francoise von Trapp (30:24):
With chiplets, we are disaggregating
right.
Pratyush Kamal (30:28):
Yeah.
Francoise von Trapp (30:29):
But we're also re-aggregating into one
device and putting everything asclose as possible to make them
more efficient.
Pratyush Kamal (30:37):
Yeah.
Francoise von Trapp (30:38):
So chiplets are also a push towards
that efficiency for AI.
Pratyush Kamal (30:43):
Yeah, yeah, individual chiplets are becoming
more efficient by themselves,but you have the added overhead
of connecting the two and youburn extra power there.
Francoise von Trapp (30:52):
Okay, so we've been talking a lot about
how important the EDA industryis to semiconductor
manufacturing.
What role does Siemens play inproviding 3D IC design tools to
the industry?
Pratyush Kamal (31:07):
Siemens is playing a very central role.
We are one of the three largeorganizations that have a whole
suite of tools to realize your3D design from concept to tape
out.
What we are doing currently istaking all of our silicon tools,
all of our packaging tools, andwe are not stopping there.
We are looking at ourmechanical design tools, for
(31:27):
example, computational fluiddynamics.
We are bringing all of theseunder a single umbrella.
We are trying to see how we canstitch them together, how we
can automate the data exchangeacross different tools by
standardizing the language theyspeak, the information that
needs to be passed on to a tool.
For example, we are veryfamiliar with the concept of
(31:48):
design kits in the silicon world.
Foundries provide the designkit and it becomes as a Lego
piece to you and then you justput those Lego pieces together
and build your chip.
In the silicon world we did notfollow that practice in
packaging till now.
Siemens is leading the efforthere across the industry is
trying to standardize thatlanguage.
We don't want to read aPDF-based design rule manual and
(32:11):
build a chip based on that.
We want to automate thatlanguage.
We want our tools one tool tounderstand the language of
another tool, whether it's fromSiemens or from Cadence or from
Synopsys.
So we are trying to makeinteroperability as a very
central to our 3D IC workflows.
We are creating loops betweendifferent tools and different
(32:32):
workflows.
What I mean by a workflow isbasically a physical design.
Workflow is essentiallyeverything relating to
physically designing that entity, whether it's a floor planning
of the chip, floor planning ofthe package.
How do you do the bumpconnections, how do you do the
interposer or the substraterouting.
It's all part of the physicaldesign workflow.
(32:53):
It doesn't stop there.
Nothing is done until youverify it.
So, of course, verification isalso part of that workflow.
So that's what I mean.
So we are trying to createthese workflows and stitch them
together as well, Because whenyou are doing a physical design,
you need to know thermal, youneed to know your signal
integrity implications.
Power is always at the centerof 3D ICs.
(33:16):
I can't put the emphasisanymore on it.
Francoise von Trapp (33:20):
To wrap things up, can you summarize
what you would want listeners totake away from this
conversation?
Maybe the three top points thatyou want to make here.
Pratyush Kamal (33:31):
I can promise my customers that, as a
representative of the EDAindustry, we understand your
challenge as well as you do.
We understand your complexityand that's why, philosophically,
the EDA industry is starting tosee the need for a
solution-focused software thanan isolated software by itself.
(33:52):
The software by itself meansnothing until it gives you a
solution right.
So we are also trying to enablean open-chiplet economy as an
EDA industry representative, andthat will allow our customers
flexibility to use best-in-classtools.
(34:13):
They won't be forced orobligated to use tools that they
don't want to, but becausethey're part of that workflow
today, they are forced to usecertain tools.
So we want to allow our usersthat flexibility tomorrow.
And the third thing is, with AIavailable as a tool to us, we
expect a future where our userswill be able to work at a higher
(34:37):
level of abstraction andbecause the workforce of
tomorrow that we see is going tobe consisting of experts with a
very deep vertical domain focus, but more of a broad focus.
And the last thing is what weunderstand is in the United
(34:57):
States, the average age of adouble E is 57.
We need a lot, many moreengineers to be able to do the
work and, as you can see, it'sreally dominated by people who
are very close to retiring, sowe'll have even more labor
challenge in future.
So EDA industry, because that'swhere the design starts.
So we are very focused onbuilding workforce of tomorrow
(35:21):
and we work very closely withthe universities in terms of
providing them educationalsoftware and training the next
generation of engineers andcreating excitement around EDA,
3d, ic and advanced packaging.
Francoise von Trapp (35:35):
So if they're learning to be a chip
package designer in school rightnow, they could possibly be
using the tools or learning onthe tools that they're going to
be using in the field.
Yeah, okay, all right.
Well, where can people go tolearn more?
Pratyush Kamal (35:50):
Please visit us at wwwsiemenscom and you will
learn about all the excitingtechnologies that we have for
you to build your nextgeneration chip.
Francoise von Trapp (36:00):
Okay, great.
Thank you so much, Pariyush.
Pratyush Kamal (36:03):
You're welcome.
Thank you, Frances.
Francoise von Trapp (36:09):
To explore how Siemens is shaping the
future of 3DIC design, head overto siemenscom slash 3DIC and
see how you can bring your nextgeneration chip designs to life.
And if you're listening priorto June 22nd and will be
attending DAC, make sure tovisit the Siemens booth on the
exhibitor floor.
There's lots more to come, sotune in next time to the 3D
Insights podcast.
(36:30):
The 3D Insights podcast is aproduction of 3D Insights LLC.
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